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Fix inconsistent EOL

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jaby
2025-01-08 22:27:37 +01:00
parent 57671ac79d
commit 1f7141c517
184 changed files with 13686 additions and 13685 deletions
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88
src/Library/internal-include/SPU/spu_internal.hpp
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@@ -1,44 +1,44 @@
#pragma once
#include <PSX/System/IOPorts/dma_io.hpp>
#include <PSX/SPU/spu.hpp>
namespace JabyEngine {
namespace SPU {
namespace internal {
struct DMA {
static void wait() {
DMA_IO::SPU.wait();
while(SPU_IO::StatusRegister.read().is_set(SPU_IO_Values::StatusRegister::TransferBusy));
}
static void end() {
SPU_IO::ControlRegister.set_transfer_mode(SPU_IO_Values::ControlRegister::Stop);
}
struct Receive {
static void prepare() {
end();
SPU_IO::DataTransferControl.write(SPU_IO_Values::DataTransferControl::NormalTransferMode());
SPU_IO::ControlRegister.set_transfer_mode(SPU_IO_Values::ControlRegister::Stop);
}
static void set_src(uintptr_t adr) {
DMA_IO::SPU.set_adr(adr);
}
static void set_dst(SPU::SRAMAdr adr) {
SPU_IO::SRAMTransferAdr.write(adr);
SPU_IO::ControlRegister.set_transfer_mode(SPU_IO_Values::ControlRegister::DMAWrite);
}
static void start(uint16_t blockCount, uint16_t wordsPerBlock = 0x10) {
using SyncMode1 = DMA_IO_Values::BCR::SyncMode1;
DMA_IO::SPU.block_ctrl.write(DMA_IO_Values::BCR::from(SyncMode1::BlockSize.with(wordsPerBlock), SyncMode1::BlockAmount.with(blockCount)));
DMA_IO::SPU.channel_ctrl.write(DMA_IO_Values::CHCHR::StartSPUReceive());
}
};
};
}
}
}
#pragma once
#include <PSX/System/IOPorts/dma_io.hpp>
#include <PSX/SPU/spu.hpp>
namespace JabyEngine {
namespace SPU {
namespace internal {
struct DMA {
static void wait() {
DMA_IO::SPU.wait();
while(SPU_IO::StatusRegister.read().is_set(SPU_IO_Values::StatusRegister::TransferBusy));
}
static void end() {
SPU_IO::ControlRegister.set_transfer_mode(SPU_IO_Values::ControlRegister::Stop);
}
struct Receive {
static void prepare() {
end();
SPU_IO::DataTransferControl.write(SPU_IO_Values::DataTransferControl::NormalTransferMode());
SPU_IO::ControlRegister.set_transfer_mode(SPU_IO_Values::ControlRegister::Stop);
}
static void set_src(uintptr_t adr) {
DMA_IO::SPU.set_adr(adr);
}
static void set_dst(SPU::SRAMAdr adr) {
SPU_IO::SRAMTransferAdr.write(adr);
SPU_IO::ControlRegister.set_transfer_mode(SPU_IO_Values::ControlRegister::DMAWrite);
}
static void start(uint16_t blockCount, uint16_t wordsPerBlock = 0x10) {
using SyncMode1 = DMA_IO_Values::BCR::SyncMode1;
DMA_IO::SPU.block_ctrl.write(DMA_IO_Values::BCR::from(SyncMode1::BlockSize.with(wordsPerBlock), SyncMode1::BlockAmount.with(blockCount)));
DMA_IO::SPU.channel_ctrl.write(DMA_IO_Values::CHCHR::StartSPUReceive());
}
};
};
}
}
}

16
src/Library/internal-include/SPU/spu_mmu.hpp
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@@ -1,9 +1,9 @@
#pragma once
#include <PSX/jabyengine.hpp>
namespace JabyEngine {
namespace SPU_MMU {
const uint8_t* allocate(uint8_t voice, size_t size);
void deallocate(uint8_t voice);
}
#pragma once
#include <PSX/jabyengine.hpp>
namespace JabyEngine {
namespace SPU_MMU {
const uint8_t* allocate(uint8_t voice, size_t size);
void deallocate(uint8_t voice);
}
}

102
src/Library/internal-include/System/callbacks_internal.hpp
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@@ -1,51 +1,51 @@
#pragma once
#include "threads.hpp"
#include <stdio.hpp>
namespace JabyEngine {
namespace Callback {
namespace internal {
static void execute_callback(Thread::Handle thread_handle, uint32_t parm) {
if(CurrentThread::is_me(MainThread::Handle)) {
CurrentThread::replace_with(thread_handle);
CurrentThread::force_a0(parm);
}
SysCall::ReturnFromException();
}
static uint32_t resume_callback(Thread::Handle handle) {
SysCall::ChangeThread(handle);
asm("sw $a0, %0" : "=m"(handle));
return handle;
}
namespace VSync {
static constexpr size_t StackSize = 64;
extern SysCall::ThreadHandle thread_handle;
extern uint32_t stack[StackSize];
void routine();
static void [[deprecated("Currently not in use")]] execute() {
execute_callback(VSync::thread_handle, 0);
}
}
namespace CD {
static constexpr size_t StackSize = 256;
extern Thread::Handle thread_handle;
extern uint32_t stack[StackSize];
void routine(uint32_t irq);
static void execute(uint32_t irq) {
execute_callback(CD::thread_handle, irq);
}
static uint32_t resume() {
return resume_callback(MainThread::Handle);
}
}
}
}
}
#pragma once
#include "threads.hpp"
#include <stdio.hpp>
namespace JabyEngine {
namespace Callback {
namespace internal {
static void execute_callback(Thread::Handle thread_handle, uint32_t parm) {
if(CurrentThread::is_me(MainThread::Handle)) {
CurrentThread::replace_with(thread_handle);
CurrentThread::force_a0(parm);
}
SysCall::ReturnFromException();
}
static uint32_t resume_callback(Thread::Handle handle) {
SysCall::ChangeThread(handle);
asm("sw $a0, %0" : "=m"(handle));
return handle;
}
namespace VSync {
static constexpr size_t StackSize = 64;
extern SysCall::ThreadHandle thread_handle;
extern uint32_t stack[StackSize];
void routine();
static void [[deprecated("Currently not in use")]] execute() {
execute_callback(VSync::thread_handle, 0);
}
}
namespace CD {
static constexpr size_t StackSize = 256;
extern Thread::Handle thread_handle;
extern uint32_t stack[StackSize];
void routine(uint32_t irq);
static void execute(uint32_t irq) {
execute_callback(CD::thread_handle, irq);
}
static uint32_t resume() {
return resume_callback(MainThread::Handle);
}
}
}
}
}

108
src/Library/internal-include/System/threads.hpp
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@@ -1,55 +1,55 @@
#pragma once
#include <PSX/System/syscalls.hpp>
namespace JabyEngine {
struct Thread {
using Handle = SysCall::ThreadHandle;
static constexpr uint32_t idx_from_handle(SysCall::ThreadHandle thread) {
return thread & 0xFFFF;
}
static uintptr_t get_pic_of(Handle handle) {
return table_of_tables.threads[idx_from_handle(handle)].epc;
}
template<size_t N>
static Handle create(void(*function)(uint32_t), uint32_t(&stack)[N]) {
return SysCall::OpenThread(reinterpret_cast<void(*)()>(function), &stack[N - 1], SysCall::get_gp());
}
static void set_kernel_mode_for(SysCall::ThreadHandle handle) {
table_of_tables.threads[idx_from_handle(handle)].sr = 0x0;
}
static void set_user_mode_for(SysCall::ThreadHandle handle) {
table_of_tables.threads[idx_from_handle(handle)].sr = 0x40000404;
}
};
struct CurrentThread {
static uintptr_t get_pic() {
return table_of_tables.processes->current_tcb->epc;
}
static void force_a0(uint32_t a0) {
table_of_tables.processes->current_tcb->reg[4] = a0;
}
static bool is_me(Thread::Handle handle) {
return table_of_tables.processes->current_tcb == &table_of_tables.threads[Thread::idx_from_handle(handle)];
}
static void replace_with(Thread::Handle handle) {
table_of_tables.processes->current_tcb = &table_of_tables.threads[Thread::idx_from_handle(handle)];
}
};
struct MainThread {
static constexpr const Thread::Handle Handle = 0xFF000000;
static uintptr_t get_pic() {
return table_of_tables.threads[0].epc;
}
};
#pragma once
#include <PSX/System/syscalls.hpp>
namespace JabyEngine {
struct Thread {
using Handle = SysCall::ThreadHandle;
static constexpr uint32_t idx_from_handle(SysCall::ThreadHandle thread) {
return thread & 0xFFFF;
}
static uintptr_t get_pic_of(Handle handle) {
return table_of_tables.threads[idx_from_handle(handle)].epc;
}
template<size_t N>
static Handle create(void(*function)(uint32_t), uint32_t(&stack)[N]) {
return SysCall::OpenThread(reinterpret_cast<void(*)()>(function), &stack[N - 1], SysCall::get_gp());
}
static void set_kernel_mode_for(SysCall::ThreadHandle handle) {
table_of_tables.threads[idx_from_handle(handle)].sr = 0x0;
}
static void set_user_mode_for(SysCall::ThreadHandle handle) {
table_of_tables.threads[idx_from_handle(handle)].sr = 0x40000404;
}
};
struct CurrentThread {
static uintptr_t get_pic() {
return table_of_tables.processes->current_tcb->epc;
}
static void force_a0(uint32_t a0) {
table_of_tables.processes->current_tcb->reg[4] = a0;
}
static bool is_me(Thread::Handle handle) {
return table_of_tables.processes->current_tcb == &table_of_tables.threads[Thread::idx_from_handle(handle)];
}
static void replace_with(Thread::Handle handle) {
table_of_tables.processes->current_tcb = &table_of_tables.threads[Thread::idx_from_handle(handle)];
}
};
struct MainThread {
static constexpr const Thread::Handle Handle = 0xFF000000;
static uintptr_t get_pic() {
return table_of_tables.threads[0].epc;
}
};
}

74
src/Library/internal-include/mipscalls.hpp
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@@ -1,38 +1,38 @@
#pragma once
#include <PSX/Auxiliary/bits.hpp>
namespace JabyEngine {
namespace MIPS {
struct SR {
static constexpr auto IEc = Bit(0); // Current Interrupt Enable (0=Disable, 1=Enable)
static constexpr auto KUc = Bit(1); // Current Kernel/User Mode (0=Kernel, 1=User)
static constexpr auto IEp = Bit(2); // Previous Interrupt Disable
static constexpr auto KUp = Bit(3); // Previous Kernal/User Mode
static constexpr auto IEo = Bit(4); // Old Interrupt Disable
static constexpr auto KUo = Bit(5); // Old Kernal/User Mode
static constexpr auto Im = BitRange::from_to(8, 15); // 8 bit interrupt mask fields. When set the corresponding interrupts are allowed to cause an exception.
static constexpr auto Isc = Bit(16); // Isolate Cache (0=No, 1=Isolate) When isolated, all load and store operations are targetted to the Data cache, and never the main memory. (Used by PSX Kernel, in combination with Port FFFE0130h)
static constexpr auto Swc = Bit(17); // Swc Swapped cache mode (0=Normal, 1=Swapped) Instruction cache will act as Data cache and vice versa. Use only with Isc to access & invalidate Instr. cache entries. (Not used by PSX Kernel)
static constexpr auto PZ = Bit(18); // PZ When set cache parity bits are written as 0.
static constexpr auto CM = Bit(19); // CM Shows the result of the last load operation with the D-cache isolated. It gets set if the cache really contained data for the addressed memory location.
static constexpr auto PE = Bit(20); // Cache parity error (Does not cause exception)
static constexpr auto TS = Bit(21); // TLB shutdown. Gets set if a programm address simultaneously matches 2 TLB entries. (initial value on reset allows to detect extended CPU version?)
static constexpr auto BEV = Bit(22); // Boot exception vectors in RAM/ROM (0=RAM/KSEG0, 1=ROM/KSEG1)
static constexpr auto RE = Bit(25); // Reverse endianness (0=Normal endianness, 1=Reverse endianness) Reverses the byte order in which data is stored in memory. (lo-hi -> hi-lo) (Has affect only to User mode, not to Kernal mode) (?) (The bit doesn't exist in PSX ?)
static constexpr auto CU0 = Bit(28); // COP0 Enable (0=Enable only in Kernal Mode, 1=Kernal and User Mode)
static constexpr auto CU1 = Bit(29); // COP1 Enable (0=Disable, 1=Enable) (none such in PSX)
static constexpr auto CU2 = Bit(30); // COP2 Enable (0=Disable, 1=Enable) (GTE in PSX)
static constexpr auto CU3 = Bit(31); // COP3 Enable (0=Disable, 1=Enable) (none such in PSX)
static uint32_t read() {
uint32_t sr;
__asm__("mfc0 %0, $12" : "=rm"(sr));
return sr;
}
static void write(uint32_t sr) {
__asm__("mtc0 %0, $12" :: "rm"(sr));
}
};
}
#pragma once
#include <PSX/Auxiliary/bits.hpp>
namespace JabyEngine {
namespace MIPS {
struct SR {
static constexpr auto IEc = Bit(0); // Current Interrupt Enable (0=Disable, 1=Enable)
static constexpr auto KUc = Bit(1); // Current Kernel/User Mode (0=Kernel, 1=User)
static constexpr auto IEp = Bit(2); // Previous Interrupt Disable
static constexpr auto KUp = Bit(3); // Previous Kernal/User Mode
static constexpr auto IEo = Bit(4); // Old Interrupt Disable
static constexpr auto KUo = Bit(5); // Old Kernal/User Mode
static constexpr auto Im = BitRange::from_to(8, 15); // 8 bit interrupt mask fields. When set the corresponding interrupts are allowed to cause an exception.
static constexpr auto Isc = Bit(16); // Isolate Cache (0=No, 1=Isolate) When isolated, all load and store operations are targetted to the Data cache, and never the main memory. (Used by PSX Kernel, in combination with Port FFFE0130h)
static constexpr auto Swc = Bit(17); // Swc Swapped cache mode (0=Normal, 1=Swapped) Instruction cache will act as Data cache and vice versa. Use only with Isc to access & invalidate Instr. cache entries. (Not used by PSX Kernel)
static constexpr auto PZ = Bit(18); // PZ When set cache parity bits are written as 0.
static constexpr auto CM = Bit(19); // CM Shows the result of the last load operation with the D-cache isolated. It gets set if the cache really contained data for the addressed memory location.
static constexpr auto PE = Bit(20); // Cache parity error (Does not cause exception)
static constexpr auto TS = Bit(21); // TLB shutdown. Gets set if a programm address simultaneously matches 2 TLB entries. (initial value on reset allows to detect extended CPU version?)
static constexpr auto BEV = Bit(22); // Boot exception vectors in RAM/ROM (0=RAM/KSEG0, 1=ROM/KSEG1)
static constexpr auto RE = Bit(25); // Reverse endianness (0=Normal endianness, 1=Reverse endianness) Reverses the byte order in which data is stored in memory. (lo-hi -> hi-lo) (Has affect only to User mode, not to Kernal mode) (?) (The bit doesn't exist in PSX ?)
static constexpr auto CU0 = Bit(28); // COP0 Enable (0=Enable only in Kernal Mode, 1=Kernal and User Mode)
static constexpr auto CU1 = Bit(29); // COP1 Enable (0=Disable, 1=Enable) (none such in PSX)
static constexpr auto CU2 = Bit(30); // COP2 Enable (0=Disable, 1=Enable) (GTE in PSX)
static constexpr auto CU3 = Bit(31); // COP3 Enable (0=Disable, 1=Enable) (none such in PSX)
static uint32_t read() {
uint32_t sr;
__asm__("mfc0 %0, $12" : "=rm"(sr));
return sr;
}
static void write(uint32_t sr) {
__asm__("mtc0 %0, $12" :: "rm"(sr));
}
};
}
}

76
src/Library/internal-include/periphery_internal.hpp
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@@ -1,39 +1,39 @@
#pragma once
#include <PSX/System/IOPorts/interrupt_io.hpp>
#include <PSX/System/IOPorts/periphery_io.hpp>
#include <PSX/Periphery/periphery.hpp>
#include <stdio.hpp>
extern "C" void busy_loop(int count);
namespace JabyEngine {
namespace Periphery {
using namespace Periphery_IO;
static void connect_to(uint16_t port) {
JOY_CTRL.write(Periphery_IO_Values::JOY_CTRL::create_for(port));
busy_loop(500);
}
static void close_connection() {
JOY_CTRL.write(Periphery_IO_Values::JOY_CTRL::close());
}
static void send_byte(uint8_t byte) {
while(!JOY_STAT.is_ready_transfer());
JOY_TX_DATA.write(Periphery_IO_Values::JOY_TX_DATA::create(byte));
}
static uint8_t read_byte() {
while(!JOY_STAT.has_response());
return JOY_RX_DATA.read().raw;
}
static void acknowledge() {
while(JOY_STAT.read().is_set(Periphery_IO_Values::JOY_STAT::ACKIrqLow));
JOY_CTRL.write(JOY_CTRL.read().set(Periphery_IO_Values::JOY_CTRL::ACK));
Interrupt::ack_irq(Interrupt::Periphery);
}
}
#pragma once
#include <PSX/System/IOPorts/interrupt_io.hpp>
#include <PSX/System/IOPorts/periphery_io.hpp>
#include <PSX/Periphery/periphery.hpp>
#include <stdio.hpp>
extern "C" void busy_loop(int count);
namespace JabyEngine {
namespace Periphery {
using namespace Periphery_IO;
static void connect_to(uint16_t port) {
JOY_CTRL.write(Periphery_IO_Values::JOY_CTRL::create_for(port));
busy_loop(500);
}
static void close_connection() {
JOY_CTRL.write(Periphery_IO_Values::JOY_CTRL::close());
}
static void send_byte(uint8_t byte) {
while(!JOY_STAT.is_ready_transfer());
JOY_TX_DATA.write(Periphery_IO_Values::JOY_TX_DATA::create(byte));
}
static uint8_t read_byte() {
while(!JOY_STAT.has_response());
return JOY_RX_DATA.read().raw;
}
static void acknowledge() {
while(JOY_STAT.read().is_set(Periphery_IO_Values::JOY_STAT::ACKIrqLow));
JOY_CTRL.write(JOY_CTRL.read().set(Periphery_IO_Values::JOY_CTRL::ACK));
Interrupt::ack_irq(Interrupt::Periphery);
}
}
}