Current buggy state
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@@ -7,8 +7,6 @@
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namespace JabyEngine {
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namespace CD {
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extern volatile uint8_t zero;
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namespace internal {
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enum struct State {
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Ready = 0,
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@@ -21,9 +19,36 @@ namespace JabyEngine {
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Error,
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};
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extern State current_state;
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extern State current_state;
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extern uint8_t irq_bit_pending;
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extern uint8_t last_cmd;
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struct NewCommand {
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struct Command {
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static void wait_completed() {
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while(const_cast<volatile uint8_t&>(irq_bit_pending));
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}
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template<typename...ARGS>
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static void send(CD_IO::Command::Desc cmd, ARGS...args) {
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Command::wait_completed();
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while(CD_IO::IndexStatus.read().is_set(CD_IO::IndexStatus::IsTransmissionBusy));
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irq_bit_pending = bit::set(irq_bit_pending, cmd.complete_irq);
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last_cmd = cmd.id;
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CD_IO::PortIndex0::change_to();
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((CD_IO::PortIndex0::ParameterFifo.write(CD_IO::ParameterFifo{args})),...);
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CD_IO::PortIndex0::CommandFifo.write(CD_IO::CommandFifo{cmd.id});
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}
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template<typename...ARGS>
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static void send_wait_response(CD_IO::Command::Desc cmd, ARGS...args) {
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Command::send(cmd, args...);
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Command::wait_completed();
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}
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};
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/*struct NewCommand {
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struct Internal {
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static void wait_completed(CD_IO::Interrupt::Type irq) {
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static const auto get_next_irq = []() -> CD_IO::Interrupt::Type {
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@@ -69,7 +94,7 @@ namespace JabyEngine {
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Internal::wait_completed(cmd.complete_irq);
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Interrupt::enable_irq(Interrupt::CDROM);
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}
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};
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};*/
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namespace IRQ {
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void process(uint32_t irq);
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@@ -93,8 +118,7 @@ namespace JabyEngine {
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void enable_CDXA(bool double_speed);
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static void pause() {
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CD_IO::PortIndex0::change_to();
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NewCommand::send(CD_IO::Command::Pause);
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Command::send(CD_IO::Command::Pause);
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}
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}
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}
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