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Share commo DMA related code for use with SPU

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jaby
2024-09-10 22:50:05 +02:00
parent 0fb71beff2
commit 2f0d972a2a
6 changed files with 70 additions and 54 deletions
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14
src/Library/internal-include/GPU/gpu_internal.hpp
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@@ -65,10 +65,10 @@ namespace JabyEngine {
GPU_IO::GP1.write(GPU_IO::Command::ResetCMDBufer());
}
namespace DMA {
struct DMA {
#ifdef __SUPPORT_PS3__
// The PS3 doesn't autoincrement the GPU MADR register so we have to do it
extern uintptr_t MADR;
static uintptr_t MADR;
#endif // __SUPPORT_PS3__
static void wait() {
@@ -79,7 +79,7 @@ namespace JabyEngine {
reset_cmd_buffer();
}
namespace Receive {
struct Receive {
static void prepare() {
GPU_IO::GP1.write(GPU_IO::Command::DMADirection(GPU_IO::DMADirection::CPU2GPU));
reset_cmd_buffer();
@@ -87,7 +87,7 @@ namespace JabyEngine {
static void set_src(uintptr_t adr) {
#ifdef __SUPPORT_PS3__
MADR = adr;
DMA::MADR = adr;
#else
DMA_IO::GPU.set_adr(adr);
#endif // __SUPPORT_PS3__
@@ -105,13 +105,13 @@ namespace JabyEngine {
#ifdef __SUPPORT_PS3__
DMA_IO::GPU.set_adr(MADR);
MADR += (blockCount * wordsPerBlock) << 2;
DMA::MADR += (blockCount * wordsPerBlock) << 2;
#endif // __SUPPORT_PS3__
DMA_IO::GPU.block_ctrl.write(DMA_IO::BCR::from(SyncMode1::BlockSize.with(wordsPerBlock), SyncMode1::BlockAmount.with(blockCount)));
DMA_IO::GPU.channel_ctrl.write(DMA_IO::CHCHR::StartGPUReceive());
}
}
}
};
};
}
}
}

8
src/Library/internal-include/SPU/spu_internal.hpp
View File

@@ -5,7 +5,7 @@
namespace JabyEngine {
namespace SPU {
namespace internal {
namespace DMA {
struct DMA {
static void wait() {
DMA_IO::SPU.wait();
}
@@ -14,7 +14,7 @@ namespace JabyEngine {
SPU_IO::ControlRegister.set_transfer_mode(SPU_IO::ControlRegister::Stop);
}
namespace Receive {
struct Receive {
static void prepare() {
SPU_IO::DataTransferControl.write(SPU_IO::DataTransferControl::NormalTransferMode());
SPU_IO::ControlRegister.set_transfer_mode(SPU_IO::ControlRegister::Stop);
@@ -36,8 +36,8 @@ namespace JabyEngine {
DMA_IO::SPU.block_ctrl.write(DMA_IO::BCR::from(SyncMode1::BlockSize.with(wordsPerBlock), SyncMode1::BlockAmount.with(blockCount)));
DMA_IO::SPU.channel_ctrl.write(DMA_IO::CHCHR::StartSPUReceive());
}
}
}
};
};
}
}
}