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jaby
2024-09-06 18:32:09 +01:00
parent 0dcd2b71a6
commit a4426ad5d2
8 changed files with 143 additions and 32 deletions
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4
src/Library/internal-include/GPU/gpu_internal.hpp
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@@ -72,7 +72,7 @@ namespace JabyEngine {
#endif // __SUPPORT_PS3__
static void wait() {
::JabyEngine::DMA_IO::GPU.wait();
DMA_IO::GPU.wait();
}
static void end() {
@@ -101,7 +101,7 @@ namespace JabyEngine {
}
static void start(uint16_t blockCount, uint16_t wordsPerBlock = 0x10) {
typedef DMA_IO::BCR::SyncMode1 SyncMode1;
using SyncMode1 = DMA_IO::BCR::SyncMode1;
#ifdef __SUPPORT_PS3__
DMA_IO::GPU.set_adr(MADR);

41
src/Library/internal-include/SPU/spu_internal.hpp
View File

@@ -1,2 +1,43 @@
#pragma once
#include <PSX/System/IOPorts/dma_io.hpp>
#include <PSX/SPU/spu.hpp>
namespace JabyEngine {
namespace SPU {
namespace internal {
namespace DMA {
static void wait() {
DMA_IO::SPU.wait();
}
static void end() {
SPU_IO::ControlRegister.set_transfer_mode(SPU_IO::ControlRegister::Stop);
}
namespace Receive {
static void prepare() {
SPU_IO::DataTransferControl.write(SPU_IO::DataTransferControl::NormalTransferMode());
SPU_IO::ControlRegister.set_transfer_mode(SPU_IO::ControlRegister::Stop);
SPU_IO::ControlRegister.set_transfer_mode(SPU_IO::ControlRegister::DMAWrite);
}
static void set_src(SPU::SRAM_Adr adr) {
DMA_IO::SPU.set_adr(adr);
}
static void set_dst(SPU::SRAM_Adr adr) {
SPU_IO::SRAMTransferAdr.write(adr);
}
// Not adjusted yet
static void start(uint16_t blockCount, uint16_t wordsPerBlock = 0x10) {
using SyncMode1 = DMA_IO::BCR::SyncMode1;
DMA_IO::SPU.block_ctrl.write(DMA_IO::BCR::from(SyncMode1::BlockSize.with(wordsPerBlock), SyncMode1::BlockAmount.with(blockCount)));
DMA_IO::SPU.channel_ctrl.write(DMA_IO::CHCHR::StartSPUReceive());
}
}
}
}
}
}